*request the AHA3580 product specification for complete details ibm is a registered trademark of ibm. comtech aha corporation comtech aha corporation product brief * AHA3580 80 mbytes/sec aldc data compression coprocessor ic the AHA3580 is a single-chip cmos lossless compression and decompression integrated circuit. the device implements the aldc compression algorithm defined by various industry standards. this algorithm is also known as adaptive lossless data compression. the device compresses, decompresses or passes data through. flex ible interfaces connect directly with various microprocessors and dma devices used in tape drive systems including scsi and fiber controllers. content addressable memory within the aldc engine eliminates external srams typically required for dictionary storage in a compression system. features performance: ? 80 mbytes/sec data compression, decompression or pass-through rate with a single 80 mhz clock 2:1 average compression ratio a four byte record length register allows record lengths up to 4 gigabytes four byte record count register allows multiple record transfers error checking in decomp ression mode reportable via an interrupt flexibility: polled or interrupt driven i/o port a/b dma interfaces include fas466, fas440 and aic-43c97c programmable polarity for dma control signals dma fifo access via microprocessor port at port a interface system interface: single-chip data compression solution programmable interrupts interfaces directly with industry standard scsi chips others: open standard aldc adaptive lossless compression algorithm complies to qic-154, ecma 222, ansi x3.280-1996 and iso 15200 standard specifications algorithm compatible to ibm aldc1-20s-ha, ibm aldc1-20s-lp and aha3520 100 pin package in 14 mm 14 mm tqfp body low power 3.3 volt device applications tape drives network communications ? wired and wireless 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 aparity[0] adata[8] adata[9] adata[10] adata[11] adata[12] gnd vdd adata[13] adata[14] adata[15] adata[0] adata[1] nc adboen adata[2] gnd vdd adata[3] adata[4] adata[5] +tie adata[6] adata[7] gnd 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 vdd acin addr[0] addr[1] addr[2] +tie ?tie bcin nc addr[3] addr[4] vdd gnd clk ?tie resetn bcout ?tie bdboen waitn 30 29 28 27 26 nc ireqn nc gnd vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 gnd bdata[7] bdata[6] bdata[5] bdata[4] bdata[3] bdata[2] vdd gnd bdata[1] bff_fe baf_ae bdata[0] bdata[15] bdata[14] bdata[13] bdata[12] vdd gnd bdata[11] bdata[10] bdata[9] bdata[8] bparity[0] bparity[1] 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 vdd gnd aparity[1] mdata[7] +tie mdata[6] mdata[5] mdata[4] mdata[3] acout nc gnd vdd mcin[0] mcin[1] mdata[2] mdata[1] mdata[0] nc 96 97 98 99 100 aff_fe aaf_ae mmode nc vdd AHA3580a-080 ptc +tie xxxxxxx mmddql 1ywwbzzzzz ccccccc note: xxxxxxx = ibm part number mm = module mfg. location; dd = device mfg. location ql = qualification level 1ywwbzzzzz = ibm assembly date code & module lot no. ccccccc = country of origin
comtech aha corporation figure 1: AHA3580 block diagram functional description major blocks in this device are the microprocessor interface, port a interface, port b interface, and the compression/decompression engine. the microproce ssor interface provides status and control informa tion by register access. port a and port b interfaces are dma ports configurable for polarity, handshaking modes, and other options. the operatin g mode establishes the direction of both the port a and port b interfaces. compression or compression pass through sets the port a interface as an in put and the port b interface as an output. conversely decompression or decompression pass through sets the port a interface as an output and the port b interface as an input. decompression output disabled mode allows the device to decompress a block of data up to a predetermined point while dumping the uncompressed data, then automatically begin outputting the remaining unco mpressed data in that block or record. a four byte record length and four byte record count registers a llow the user to partition the data into multiple records to process. compression pass through mode and decompression pass through modes allow data transfers through the device without changing the data. both the port a in terface and port b interface have 16-byte fifos. port a and port b have two selectable dma modes, fas466 and aic-43c97c. fas466 mode operates as slave on port a and master on port b. the aic-43c97c mode is, more explicitly, scsi initiator synchronous mode and operates as master on port a and slave on port b. aparity[1:0] adata[15:0] clock acout acin aaf_ae bparity[1:0] bdata[15:0] bcout bdboen bcin mcin[1:0] waitn addr[4:0] mmode resetn ireqn adboen aff_fe bff_fe mdata[7:0] baf_ae port a dma state machine clock generation port b dma state machine processor interface state machine processor interface port a interface port b interface AHA3580 compression chip aldc core ibm? ibm is a registered trademark of ibm.
comtech aha corporation the aldc compression algorithm the aldc (adaptive lossless data compression) algorithm is one variant of the lz1 (lempel-ziv 1) class of data compression algorithms, first proposed by abraham lempel and jacob ziv in 1977. lz1 algorithms achieve compression by building and maintaining a data structure, called a historybuffer. an lz1 encode process and an lz1 decode process both initialize this structure to the same known state, and update it in an identical fashion. the encoder does this using the input data it receives for compressio n, while the decoder generates an identical data stream as its output, which it also uses for the update process. the compression process consists of examining the incoming data stream to identify any sequences or strings of data bytes which already exist in the encoder history. if an identical such history is available to a decoder, this matching string can be encoded and output as a 2 element copypointer, containing a byte count and history location. it is then possible for a decoder to reproduce this string exactly, by copying it from the given location in its own history. if the copypointer can be encoded in fewer bits of information than required for the data string it specifies, compression is achieved. if an incoming byte of data does not form part of a matching string, a literal, containing this embedded value, is encoded and then output to explicitly represent this byte. a decoder performs the inverse operation by first parsing a compresse d data stream into literals and copypointers for processing. aldc is a lossless algor ithm, insuring that the decompressed data output is exactly the same as the uncompressed data inpu t. qic-154 development standard describes this industry standard algorithm in detail. port a and port b configuration port a and port b are 16-bit bidirectional data ports with parity checking and generation.the ports are controlled by the configuration registers acnf[15:0] and bcnf[15:0], and polarity registers apol[7:0] and bpol[7:0]. table 1: port a interface signals table 2: port b interface signals signal name aic-43c97c fas466 apol bit direction acin dacka dreqa 7 i acout dreqa dacka 5 o adboen deasserted adboen 3 o aff_fe not used aff_fe 1 i aaf_ae not used aaf_ae 0 i signal name fas466 aic-43c97c bpol bit direction bcin dackb dreqb 7 i bcout dreqb dackb 5 o bdboen bdboen deasserted 3 i bff_fe bff_fe not used 1 o baf_ae baf_ae not used 0 o
www.aha.com e-mail: sales@aha.com comtech aha corporation pb3580_0104 ? 2005 comtech aha corp. comtech aha corporation 1126 alturas drive fax: 208.892.5601 tel: 208.892.5600 moscow id 83843-8331 a subsidiary of comtech te lecommunications corporation systems applications a typical application fo r the AHA3580 is the implementation of data comp ression in a tape drive system. an in-line architecture is employed in this system. the in-line applicatio n inserts compression directly between the host an d the system data buffer. there is no direct connection between the buffer and the host. for compress ion, data flows from the host, through the bus controller and into the AHA3580. the data is then compressed by the aldc engine and flows in to the system buffer followed by the tape drive interface. this data flow is usually controlled by a local microprocessor. for decompression, the flow is reversed. in an in-line architecture the aha compression chip operates at the data rate of the host interface controller. the AHA3580 device supports a sustained data transfer rate of up to 80 mbytes/sec. in a look-aside applicatio n, the system buffer is in series with the data flow. there is a direct connection between the host and the buffer memory through a dma port. for co mpression, data flows from the host, through the bus interface and peripheral controller and into the system buffer. data then flows from the system buffer into the AHA3580 where it is compressed and sent back to the system buffer. finally, data is transferred from the system buffer interface. during decompression, this flow is reversed. example in-line application example look-aside application ordering information about aha comtech aha corporation (aha) develops and markets superior integrated circuits, boards, and intellectual property core technology for communications systems architects worldwide. aha has been setting the st andard in forward error correction and lossless data compression technology for many years and provides flexible, cost-effective solutions for today?s growing bandwidth and reliability challenges. comtech aha corporation is a who lly owned subsidiary of comtech telecommuncations corp. (nasdaq: cmtl). for more informa tion, visit www.aha.com. AHA3580 data compression interface chip bus scsi or atapi controller buffer dram system processor system memory controller tape drive interface AHA3580 data compression interface chip bus scsi or atapi controller buffer dram system processor system memory controller peripheral controller data flow control part number description AHA3580a-080 ptc 80 mbytes/sec aldc data compression coprocessor ic
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